My Resume

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Resume for Eric R. Brodeur
5011 30th Ave South, Minneapolis MN 55417
(206) 999–6594
erb@chezbrodeur.net


SUMMARY:

Diagnostic and manufacturing testing experience with ATM switching fabrics, network processors, SONET hardware, various networking and routing ASIC designs, supercomputer architectures, clustered disk storage systems, manufacturing systems testing.
Experienced with C, Assembly (x86, i960, PPC), Python, Bash, Linux, FreeBSD, ClearCase, CVS, Subversion.


EDUCATION:

1989 – 1993

B.S.E.E., Magna Cum Laude, Rose-Hulman Institute of Technology, Terre Haute IN

1993 – 1995

Course work towards M.S.E.E., Northeastern University, Boston MA

1995 – 1996

Course work towards M.A., Education, University of Massachusetts, Amherst MA


WORK HISTORY:

Isilon11/2005 – 05/2008, 01/2010 – Present

Software Development Engineer II
EMC Corporation, Plymouth MN
Software Development Engineer II
Isilon Systems Inc, Seattle WA, Plymouth MN
Manufacturing test code development and support for Isilon IQ Clustered Storage systems

Wolfram05/2008 – 01/2010

Quality Assurance Engineer
Wolfram Research Inc, Champaign IL

Cray02/2004 – 11/2005

Software Engineer
Cray Inc, Seattle WA
Diagnostics development and hardware debug on Red Storm XT3 Supercomputer

08/2003 – 02/2004

Diagnostic Engineer
Mangrove Systems, Wallingford CT
Diagnostics development for early prototype hardware

CienaWaveSmith09/2001 – 08/2003

Senior Lead Diagnostic Engineer
CIENA, Acton MA
Principal Diagnostic Engineer
WaveSmith Networks, Acton MA
WaveSmith Networks was acquired by CIENA in June, 2003
Diagnostics for various switch fabric and PHY modules on DN4100 and DN7100

Lucent05/1999 – 09/2001

Principal Diagnostic Engineer
Lucent Technologies INS, InterNetworking Systems, Westford MA
Lucent Technologies ONG, Optical Networking Group, Acton MA
Ignitus Communications, Acton MA
Ignitus was acquired by Lucent ONG in March, 2000
Lucent ONG: Diagnostics for Ignitus 3500 switch
Lucent INS: Diagnostics for MSC25000, GX550 OC48c BIO module

AscendCascade11/1996 – 05/1999

Senior Diagnostic Engineer
Lucent Technologies INS, Westford MA
Ascend Communications, Westford MA
Cascade Communications, Westford MA
Diagnostics for CBX500, GX550, GX250, MSC25000

MAJOR TASKS / PROJECTS:

  • Isilon Systems Inc Manufacturing Testing:

    Maintained and enhanced manufacturing test suite for entire Isilon IQ product family, working with Manufacturing team and Contract Manufacturer to quickly adopt new hardware and features, resolve problems on CM test floor impacting production, and improve test coverage, reliability, and quality. Hardware includes various vendor motherboards, 3Ware / LSI / Vitesse disk controllers, PATA / SATA / SAS hard drives, Gigabit Ethernet and InfiniBand network technologies, proprietary Isilon PCI hardware cards.

  • Cray Inc XT3 Supercomputer:

    Worked with CRMS / RAS Team (Cray RAS and Management System; Reliability, Availability, Serviceability). Provide diagnostics for the compute processors (AMD Opteron processors), and the SeaStar high speed router ASIC. Many of these diagnostics were ported from DV test suites used by the hardware and design teams. Helped debug systems in-house and at customer sites.

  • WaveSmith / Ciena DN-2100/4100/7100/8100, CFM, HCFM:

    Worked on various switching fabrics for ATM / Multiservice architectures, including Lucent / Agere APC OC12-thread traffic manager, Vitesse PaceMaker 2.5 / 3.0 OC48-thread traffic manager, proprietary FPGA-based fabrics, and IBM PRS-64Gu 40G+ fabric. Diagnostic development and card bringup for DS3 IMA PHY card.

  • OC48c BIO Board for Lucent GX550:

    Ported code elements from various other projects to create a patchwork diagnostic for board in minimal time, since board was already in-house and needed debug, but no diags were available. Worked on this board, and corresponding testcard for next-generation GX550 OC48c-thread based switch fabric, for the bulk of the time spent at Lucent INS, from 9/00 to 9/01.

  • Ignitus 3500 ATM / SONET Metro Switch:

    Wrote diagnostics using 860, 750 PPC processors; RTOS (VxWorks); SONET ADM technology; Lucent / Agere APC traffic manager. Developed CLI / menu / scripting shell, and manufacturing diagnostics infrastructure; system level sync & messaging on Ethernet layer.

  • Ascend / Lucent MSC25000:

    Assisted in early architecture phase of next-generation multi-protocol product, contributing to online fault detection discussions. Wrote Diagnostic Architecture, Functional Specs for system testing approach of switch.

  • Ascend GX250 PHY Shelf (aka Lucent GX550 Shelf Extender):

    Wrote low-level interrupt-driven message-passing protocol and driver for passing commands, status, data over an optical FPGA-controlled “fiber channel.” Added functionality to i960 boot ROM of a slave device on the GX250 such that the master device on GX550 could update FLASH application code over fiber channel / protocol.

  • Ascend GX550 Switch Fabric Module:

    Wrote suite of tests and utilities with HW Engineer for HVT / Manufacturing purposes for Lucent Atlanta ASC/ACE based 25 Gbps switch fabric. Programmed testing HW designed with ASIC, FPGA, ATMizerII, XBERT chips for full 100% HW testing with greater control than using GX550 Base IO (BIO) units directly. Tests included: Thread To Thread; Cell Path; Multicast; Many-to-One; Backpressure; False Backpressure; Latency; Congestion; Full Bandwidth.

    Testing approach: Wrote generic SW / HW interface to facilitate test writing, modification, allowing user to “write their own tests” by setting SW parameters and “programming” the HW. Wrote menu / cursor based UI for this purpose. Error logging routines needed to be modified to handle the volume of possible errors during a single test run. Development and debug time of mfg diag test suite was ultimately minimized with this generic testing approach.

  • Cascade CBX500 Cell-Frame-Cell (CFC) Module:

    Wrote Shared Memory testing with Intel i960, 2 LSI ATMizerIIs, and 2 Motorola PPCs; SMEM Virtual UART command-passing protocol for the five processors; Sleep/Awake procedure with VUART for shared memory testing by individual processors. Updated ATMizerII boot ROM code for new hardware cards, mostly with respect to shared memory code, and bootstrap procedure for booting in Cell Buffer RAM.


This document © 2011 by Eric Brodeur.
Unauthorized reproduction or distribution expressly prohibited.
References Available Upon Request
Updated January, 2011